The conductivity of narrow copper (Cu)-filled vias in current high density wiring technology is degraded by the small grain size of the Cu in vias of these dimensions. Conventional techniques involve annealing the Cu-containing structure to grow the grain size and thus improve the conductivity.
For example, in general, conventional techniques used for fabricating a Cu-filled via typically involve first forming a via hole in a dielectric matrix in which the wiring structure is embedded. Second, the via hole is lined with a diffusion barrier to prevent the diffusion of Cu into the dielectric. This diffusion barrier typically includes tantalum nitride (TaN) deposited directly onto the dielectric, and tantalum (Ta) deposited on top of the TaN. Third, a thin layer of seed Cu is sputter deposited onto the exposed Ta surface, in order to prepare the via for electroplating. Fourth, an electroplating process is used to fill the via with Cu. Fifth, the resulting structure is annealed to grow the Cu grains in the via and improve the conductivity. This approach, however, has proven to be of limited effectiveness for these Cu via structures in terms of enhancing conductivity.
A limiting factor for the growth of large Cu grains is the size of the grains in the seed Cu layer. These grains in the seed Cu form a template upon which the electroplated Cu is subsequently deposited, and the grain size of the initially electroplated Cu thus reflects the small grain size exhibited by the seed Cu layer. Annealing subsequent to Cu electroplating is of only limited effectiveness in overcoming the initial small grain structure. The small grain size exhibited by the seed Cu layer is in great part the result of the thinness of this layer, along with the degree to which the Cu wets the underlying diffusion barrier surface. The seed Cu layer thickness cannot be increased to overcome this problem because the seed Cu, being formed by a sputtering process, is not deposited conformally. Thus if the seed Cu is made too thick in an attempt to increase its grain size, it will tend to pinch off the openings to via in the wiring structure, rendering subsequent successful electroplating impossible.
Therefore, techniques for improving the conductivity of Cu-filled vias would be desirable.